Stage 1
| Task | Owner | Status |
|---|---|---|
| Sample | Nikhil |  |
| Setup a basic page using the relevant technologies like npm, babel and webpack | Rikhil |  |
| On the left side we have a basic menu and it should have a link called library | Rikhil | |
| On click of this link, we should display the hello library page on the right side | Rikhil | |
| Nikhil should be able to take this code and run on his machine |
hi nikhil, can you help me in codes of ngspice windows please.
You want to setup the ngspice on windows or your query is regarding something else?
I have ngspice setup on windows but I do not get that how to include technology files in ngspice on windows. Command line which I used is “.include 16nmHP.pm”
I have the code on ngspice and it’s working. Logic is okay too but there is some voltage issue. I really need help.
Here it is:
*Transient Analysis of CMOS XOR
.model nmos nmos level = 54 version = 4.7
.model nmos nmos level = 54 version = 4.7
.param psu = 0.9V
.param len = 16n
.param wpmos=100n wnmos=50n
vsupply vdd 0 {psu}
vgnd vss 0 0V
*Inputs to transistors
vina va vss PULSE(0 {psu} 1NS 1NS 1NS 20NS 400NS)
vinb vb vss PULSE(0 {psu} 4NS 4NS 4NS 60NS 100NS)
*Function for XOR
******************MOSFETs drain gate source body
*inverters for inputs(a b)
Mpa vabar va vdd vdd pmos l={len} w={wpmos} ; pmos
Mna vabar va vss vss nmos l={len} w={wnmos} ; nmos
Mpb vbbar vb vdd vdd pmos l={len} w={wpmos} ; pmos
Mnb vbbar vb vss vss nmos l={len} w={wnmos} ; nmos
*xor inputs(a b)
Mp1 vdr1 vabar vdd vdd pmos l={len} w={wpmos} ; pmos
Mp2 vout vb vdr1 vdd pmos l={len} w={wpmos} ; pmos
Mp3 vdr2 va vdd vdd pmos l={len} w={wpmos} ; pmos
Mp4 vout vbbar vdr2 vdd pmos l={len} w={wpmos} ; pmos
Mn1 vout vabar vdr3 vss nmos l={len} w={wpmos} ; nmos
Mn2 vout vb vss vdr3 nmos l={len} w={wpmos} ; nmos
Mn3 vdr3 va vss vss nmos l={len} w={wpmos} ; nmos
Mn4 vdr3 vbbar vss vss nmos l={len} w={wpmos} ; nmos
Cload vout vss1 200f
vdc0 vss1 vss dc 0V
.options method=gear reltol=0.1m
.tran 0.1n 200n 0 0.1n
.save all @vsupply[p]
.control
run
let isteady = i(vsupply)*i(vsupply)
meas tran iave INTEG isteady from=0ns to=200ns
let power = (sqrt(iave/200ns))*0.7
meas tran t1 TRIG va VAL=0.45 rise=1 TARG vout VAL=0.45 rise=1
meas tran t2 TRIG va VAL=0.45 fall=1 TARG vout VAL=0.45 fall=1
meas tran t3 TRIG vb VAL=0.45 rise=1 TARG vout VAL=0.45 rise=1
meas tran t4 TRIG vb VAL=0.45 fall=1 TARG vout VAL=0.45 fall=1
let delaya = (t1+t2)/2
let delayb = (t3+t4)/2
set filetype = ascii
write output.raw v(va) v(vout)
plot v(va) v(vout) v(vb)
print power delaya delayb
.endc
.End
Can you post the screen shot of the directory from where you are running the ngspice. At first look it looks like a wrong path issue. Please provide the screen shot for ngspice binary and the directory where you have the 16nmHP.pm file. You can also provide the absolute path to this file. Do let me know your findings.
Hello Garvita,
1.Please note that we have to add technology files before simulation. You have used 16nm length without any technology files. Hence the issue.
2.Regarding the code which you have send, width of nmos is represented using “wpmos” instead of “wnmos”.
3.Please check the connections of XOR gate. It seems something went wrong over there too.
4. You have to insert a CMOS inverter to get XOR output. Else the output vout will be of XNOR.
Please find the code below which I have updated to get the output.
*Transient Analysis of XNOR
.include tf130.pm ; LP stands for Low Power. It has high tox and high vth values. nmos1 and pmos1 refers to this file
.param psu = 1.2V
.param len = 130n
.param wpmos=2500n wnmos=1000nvsupply vdd 0 {psu}
vgnd vss 0 0V*Inputs to transistors
vina va vss PULSE(0 {psu} 1NS 1NS 1NS 20NS 400NS)
vinb vb vss PULSE(0 {psu} 4NS 4NS 4NS 60NS 100NS)*Function for XOR
******************MOSFETs drain gate source body
*inverters for inputs(a b)
Mpa vabar va vdd vdd pmos l={len} w={wpmos} ; pmos
Mna vabar va vss vss nmos l={len} w={wnmos} ; nmosMpb vbbar vb vdd vdd pmos l={len} w={wpmos} ; pmos
Mnb vbbar vb vss vss nmos l={len} w={wnmos} ; nmos*xor inputs(a b)
Mp1 vdr1 vabar vdd vdd pmos l={len} w={wpmos} ; pmos
Mp2 vdr1 vb vdd vdd pmos l={len} w={wpmos} ; pmos
Mp3 vout va vdr1 vdd pmos l={len} w={wpmos} ; pmos
Mp4 vout vbbar vdr1 vdd pmos l={len} w={wpmos} ; pmosMn1 vout vabar vdr2 vss nmos l={len} w={wnmos} ; nmos
Mn2 vdr2 vb vss vss nmos l={len} w={wnmos} ; nmos
Mn3 vout va vdr3 vss nmos l={len} w={wnmos} ; nmos
Mn4 vdr3 vbbar vss vss nmos l={len} w={wnmos} ; nmosCload vout vss1 200f
vdc0 vss1 vss dc 0V.options method=gear reltol=0.1m
.tran 0.1n 200n 0 0.1n
.save all @vsupply[p].control
run
write output.raw
plot v(va) v(vout) v(vb)
.endc
.End
File tf130.sp
- Customized PTM 130nm NMOS
.model nmos nmos level = 54
+version = 4.2.1 binunit = 1 paramchk= 1 mobmod = 0
+capmod = 2 igcmod = 1 igbmod = 1 geomod = 1
+diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1
+permod = 1 acnqsmod= 0 trnqsmod= 0
parameters related to the technology node
+tnom = 27 epsrox = 3.9
+eta0 = 0.0092 nfactor = 1.5 wint = 5e-09
+cgso = 2.4e-10 cgdo = 2.4e-10 xl = -6e-08parameters customized by the user
+toxe = 2.25e-09 toxp = 1.6e-09 toxm = 2.25e-09 toxref = 2.25e-09
+dtox = 6.5e-10 lint = 1.05e-08
+vth0 = 0.388 k1 = 0.474 u0 = 0.05852 vsat = 100370
+rdsw = 200 ndep = 1.6e+18 xj = 3.92e-08secondary parameters
+ll = 0 wl = 0 lln = 1 wln = 1
+lw = 0 ww = 0 lwn = 1 wwn = 1
+lwl = 0 wwl = 0 xpart = 0
+k2 = 0.01 k3 = 0
+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2
+dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0
+dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1.0e-009
+dvtp1 = 0.1 lpe0 = 0 lpeb = 0
+ngate = 2e+020 nsd = 2e+020 phin = 0
+cdsc = 0.000 cdscb = 0 cdscd = 0 cit = 0
+voff = -0.13 etab = 0
+vfb = -0.55 ua = 6e-010 ub = 1.2e-018
+uc = 0 a0 = 1.0 ags = 1e-020
+a1 = 0 a2 = 1.0 b0 = 0 b1 = 0
+keta = 0.04 dwg = 0 dwb = 0 pclm = 0.04
+pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5
+pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007
+fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2.3e+006
+rsh = 5 rsw = 85 rdw = 85
+rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0
+prwb = 6.8e-011 wr = 1 alpha0 = 0.074 alpha1 = 0.005
+beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002
+egidl = 0.8Customized PTM 130nm PMOS
.model pmos pmos level = 54
+version = 4.2.1 binunit = 1 paramchk= 1 mobmod = 0
+capmod = 2 igcmod = 1 igbmod = 1 geomod = 1
+diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1
+permod = 1 acnqsmod= 0 trnqsmod= 0
parameters related to the technology node
+tnom = 27 epsrox = 3.9
+eta0 = 0.0092 nfactor = 1.5 wint = 5e-09
+cgso = 2.4e-10 cgdo = 2.4e-10 xl = -6e-08parameters customized by the user
+toxe = 2.35e-09 toxp = 1.6e-09 toxm = 2.35e-09 toxref = 2.35e-09
+dtox = 7.5e-10 lint = 1.05e-08
+vth0 = -0.337 k1 = 0.433 u0 = 0.00796 vsat = 70000
+rdsw = 240 ndep = 1.22e+18 xj = 3.92e-08*secondary parameters
+ll = 0 wl = 0 lln = 1 wln = 1
+lw = 0 ww = 0 lwn = 1 wwn = 1
+lwl = 0 wwl = 0 xpart = 0
+k2 = -0.01 k3 = 0
+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2
+dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0
+dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-009
+dvtp1 = 0.05 lpe0 = 0 lpeb = 0
+ngate = 2e+020 nsd = 2e+020 phin = 0
+cdsc = 0.000 cdscb = 0 cdscd = 0 cit = 0
+voff = -0.126 etab = 0
+vfb = 0.55 ua = 2.0e-009 ub = 0.5e-018
+uc = 0 a0 = 1.0 ags = 1e-020
+a1 = 0 a2 = 1 b0 = -1e-020 b1 = 0
+keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12
+pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = 3.4e-008 drout = 0.56
+pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 9.58e-007
+fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2.3e+006
+rsh = 5 rsw = 85 rdw = 85
+rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 3.22e-008
+prwb = 6.8e-011 wr = 1 alpha0 = 0.074 alpha1 = 0.005
+beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002
+egidl = 0.8+aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002
+nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004
+eigbinv = 1.1 nigbinv = 3 aigc = 0.69 bigc = 0.0012
+cigc = 0.0008 aigsd = 0.0087 bigsd = 0.0012 cigsd = 0.0008
+nigc = 1 poxedge = 1 pigcd = 1 ntox = 1+xrcrg1 = 12 xrcrg2 = 5
+cgbo = 2.56e-011 cgdl = 2.653e-10
+cgsl = 2.653e-10 ckappas = 0.03 ckappad = 0.03 acde = 1
+moin = 15 noff = 0.9 voffcv = 0.02+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5
+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0
+at = 33000+fnoimod = 1 tnoimod = 0
+jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1
+ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1
+jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1
+ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1
+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1
+cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010
+mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5
+pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1
+cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001
+tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001
+xtis = 3 xtid = 3+dmcg = 0e-006 dmci = 0e-006 dmdg = 0e-006 dmcgt = 0e-007
+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008+rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15
+rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1
Thanks
Smita
Thankyou so much ma’am for your help. It would be really nice if you could just help me with one more thing. I am working on 16nm technology. Can you tell me the latest technology that is being used nowadays? If you don’t mind, can you please share that technology file too. It would really mean a lot.
Thankyou ma’am. I did go through the link but there are just too many and I can’t decide which one to use. What might be your suggestion for a lesser advanced technology than 16nm?
Hello garvita,
For functionality testing of digital CMOS circuits, a higher technology like 130nm will be sufficient. For research based testing, you can opt for lower technologies. Please check your requirement while choosing technology.
Thanks
Smita
Thankyou so much again, ma’am. I just have one more doubt. What’s the concept of calculating power and delay in ngspice?
